1. Field of the Invention
The present invention generally relates to a column selection signal generator of a semiconductor memory device, and more specifically, to a technology of maintaining a predetermined pulse width of a column selecting signal regardless of change of process and external conditions by selectively using a self-generated pulse signal and a pulse signal in response to an external clock signal as a column selection signal.
2. Description of the Related Art
In general, a semiconductor memory device, which stores data in a plurality of cells or reads stored data, comprises a plurality of word lines, a plurality of bit lines, a circuit for selecting the word line and the bit line, a plurality of sense amplifiers, and a row decoder and a column decoder for selecting the cell.
Specifically, the column decoder decodes a column address to output a column selection signal to select a bit line. Here, a pulse width of the column selection signal means a transmission time of data in the sense amplifier to a data bus at a read mode.
As a result, as the pulse width of the column selection signal becomes smaller, the speed of the semiconductor memory device is improved. However, when the pulse width is too small, a time for sufficiently transmitting data is not secured, which causes defects. Therefore, it is important to secure a column selection signal having a proper pulse width.
FIG. 1 is a diagram illustrating a conventional column selection signal generator of a semiconductor memory device. The conventional column selection signal generator comprises a command combination unit 10, a pulse generating unit 20 and a driving unit 30.
The command combination unit 10 comprises inverters IV1˜IV3, and a NAND gate ND1. Each of the inverters IV1˜IV3 inverts an internal read command signal IRD, an internal write command signal IWT and an internal column address selection signal ICAS, respectively. The NAND gate ND1 performs a NAND operation on output signals from the inverters IV1˜IV3 to output a pulse signal OUT2. Here, the internal read command signal IRD, the internal write command signal IWT and the column address ICAS are signals based on an external clock signal. The internal read command signal IRD is enabled at a read command, and the internal write command signal IWT is enabled at a write command. The command combination unit 10 outputs the pulse signal OUT2 in response to the internal read command signal IRD/internal write command signal IWT when a first address is applied at the read/write commands, and in response to the internal column address selection signal ICAS when a second address is applied.
The pulse generating unit 20 self-generates a pulse signal OUT1. The pulse generating unit 20 comprises a RC delay unit, a plurality of inverter delay units, a plurality of NAND gates, a plurality of inverters and a switching element. That is, the pulse generating unit 20 delays the pulse signal OUT2, and then latches the delayed signal through a latch unit which comprises the plurality of NAND gates or feeds the delayed signal back to the delay unit. Here, a pulse width of the pulse signal OUT1 is determined by delay of the plurality of delay units in the pulse generating unit 20, which are embodied with a RC circuit and an inverter chain.
The driving unit 30, which comprises inverters IV4 and IV5 connected serially, drives the pulse signal OUT1 outputted from the pulse generating unit 20 to output a column selection signal YSP. The column selection signal YSP determines a time and a period to enable a main amplifier (not shown) for amplifying data of a selected column and a main output driver (not shown.)
For example, when the column selection signal YSP generated by the internal read command signal IRD is enabled, the main amplifier (not shown) is enabled while the column selection signal YSP is enabled. Thereafter, when the column selection signal YSP is disabled, the main output driver (not shown) is enabled to determine a time for externally transmitting data of a memory cell depending on a pulse width of the column selection signal YSP. As a result, the column selection signal YSP is required to have a proper pulse width so as to sufficiently transmit the data of the memory cell to the outside.
However, the conventional column selection signal generator uses as the column selection signal YSP the pulse signal OUT1 outputted by the pulse generating unit 20 comprising a R-C delay unit (not shown). Here, since the R-C delay unit (not shown) is sensitive to change of external conditions such as process change and temperature change, the pulse width of the pulse signal OUT1 is changed depending on the change of the external condition, so that the pulse width of the column selection signal YSP is changed.